A typical magnetic disk drive digital storage system includes a read/write head system that controls the reading of information from and the writing of information to the magnetic disk. A servo system of the read/write head system controls the positioning of a read/write head relative to the disk when reading information from and writing information to the disk. FIG. 1 illustrates a block diagram of a typical servo circuit 1 of a typical disk drive read/write head system (not shown). The servo circuit 1 operates in two modes, namely, a normal mode of operations during which real data 2 is read from or written to the disk (not shown) and a test mode during which test patterns generated by a test pattern generator 4 are used to test the servo control logic 6 of the servo circuit 1.
During the normal mode of operations, the test mode signal 7 is deasserted and the multiplexer (MUX) 5 selects the real data 2 for processing by the servo control logic 6. Once the servo circuit 1 has been incorporated into a disk drive system, the test mode signal typically remains deasserted at all times such that the MUX 8 always selects real data 2 read from the disk drive and processed by the read channel preprocessing circuitry (not shown).
Prior to incorporating the servo circuit 1 into a disk drive system, the servo control logic 6 is tested to determine whether it is operating correctly. In order to test the servo control logic 6, the test mode signal 7 is asserted and the multiplexer 5 selects the test patterns generated by the pattern generator 4 for processing by the servo control logic 6. The servo control logic 6 processes the test patterns and generates output signals that are compared by a signal comparator 8 with stored signatures to determine whether the servo control logic 6 is operating correctly.
During testing, the servo control logic 6 attempts to detect certain patterns, or fields, within the test patterns generated by the test pattern generator 4. One of these patterns is a preamble pattern typically referred to as the best phase select (BPS) pattern. Another of these patterns is a sync mark pattern. The BPS pattern typically contains all binary 1's and precedes the sync mark pattern. The sync mark pattern is a pattern of binary 1's and 0's. Because the BPS pattern contains all 1's, it is a very regular pattern having peak amplitude values that are easily detected by the servo control logic 6. The peaks of the BPS pattern have a fixed phase relationship to the peaks of the sync mark pattern. Once the servo control logic 6 determines the phase of the peaks of the BPS pattern, the servo control logic 6 can locate the sync mark pattern by using the known phase relationship between the peaks of the BPS pattern and the peaks of the sync mark pattern. The sync mark pattern identifies the track at which the read/write head is located.
One known technique for generating the BPS and sync mark patterns for testing the servo control logic 6 involves generating a pseudo-random bit stream. In theory, a pseudo-random bit stream will contain a variety of different patterns of 1's and 0's. However, because the patterns are pseudo-random, many clock cycles may occur before the pattern that the servo control logic 6 is trying to detect appears. If a pattern that the servo control logic 6 is trying to detect does not appear within a certain time period, the state machine of the servo control logic 6 typically moves to a subsequent state and begins trying to detect a different pattern. For example, if the servo control logic 6 does not detect a BPS pattern within a certain time period, the servo control logic 6 will typically bypass the BPS pattern detection state. When the servo control logic 6 bypasses the BPS pattern detection state, it enters the sync mark detection state, during which the servo control logic 6 begins trying to detect the sync mark pattern. Therefore, in this case, the ability of the servo control logic 6 to detect the BPS pattern is not tested, which of course is a problem.
Another known technique for generating BPS and sync mark patterns involves generating bit patterns that are similar or identical to the types of patterns that would be read from the disk and processed by the read channel preprocessing circuitry (i.e., the preamplifier, analog-to-digital converter, etc.). With this technique, the pattern generator 4 generates real bit streams containing BPS and sync mark patterns and the servo control logic 6 attempts to detect the BPS and sync mark patterns. This technique generally ensures that none of the states of the state machine of the servo control logic 6 will be bypassed, and thus that the ability of the servo control logic 6 to detect all of the patterns will be tested. However, generating these real bit streams involves mathematical convolution, which requires expensive hardware that consumes a large area on the IC that contains the pattern generator 4.
Accordingly, a need exists for a test pattern generator that is relatively simple and inexpensive to implement and that ensures that the ability of the servo control logic to detect desired patterns will not go untested.